FIG. 10A is a block diagram of a conventional memory device 1000. A conventional memory device can be a quad data rate (QDR) type static random access memory (SRAM) type device, such as that manufactured by Cypress Semiconductor Corporation of San Jose, Calif., U.S.A. Conventional memory device 1000 can include one address port 1002, a read data port (Q) 1004 and a write data port (D) 1005. An address port 1002 can be a 28-bit wide address port (×28), while data ports (1004, 1005) can be 18-bit or 36-bit wide data ports. It is understood that data ports (1004, 1005) are unidirectional ports, providing one-way input or output data paths. Operations for conventional memory device 1000 are shown in FIGS. 10B and 10C.
FIG. 10B is a table showing two possible conventional modes of operation shown as B4A1 and B2A2. In the table, “DATA BURST” shows how long a data burst (set of consecutive data values) can be in the mode. “#ADD/CYCLE” shows the number of addresses received in a timing cycle. “# READ PORTS” shows the number of available read ports. “# WRITE PORTS” shows the number of available write ports “I/O WIDTH” shows a bit width for data values.
Mode B4A1 involves a burst of four data values in response to a single address value. In such a mode, a memory device can read or write a burst of four data values at one bank in response to one address.
Mode B2A2 involves bursts of data values, each in response to one of two address values. In such a mode, a memory device can read or write two bursts of two data values in response to two addresses.
FIG. 10C is a timing diagram showing one example of a B2A2 type mode of operation. At time t0, a read operation can start with a first address value (ADD0) being latched on a rising edge of a timing clock CLK. Subsequently, at times t4 and t5 a burst of two data values Q00 and Q01 can be output on a read port Q.
At time t1, a write operation can start with a second address value (ADD1) being latched on a falling edge of timing clock CLK. At the same time, a first write data value (D10) of a two value burst can be provided on write port D. At time t2, a second write data value (D11) of the burst can be provided on write port D.